1. Field of the Invention
The present invention relates to a method of erasing data in a non-volatile semiconductor memory device.
2. Description of the Background Art
Conventionally, when a data stored in an electrically data-erasable and rewritable non-volatile semiconductor memory device is erased, a data erase operation has been performed after data is initially written into all memory cell transistors (hereinafter, also simply referred to as memory cell) so as to set all memory cells in a data-written state (a state in which prescribed data has been written) (hereinafter, also referred to as write-before-data-erase).
Generally, as a threshold voltage of a memory cell is varied depending on a state of data write, various threshold values tend to be present. In other words, distribution of threshold voltages of the memory cells is widespread. Accordingly, unless the threshold voltages are accommodated within a certain range through write-before-data-erase before a data erase operation, distribution of the threshold voltages becomes further widespread due to a data erase operation for the memory cell.
On the other hand, if distribution of the threshold voltages of the memory cells is widespread, that is, when the threshold voltages are various, erroneous data is read from a memory cell in a data read operation. Namely, in order to secure a data read margin, suppression of variation is an important issue.
In order to address this issue, a data erase method capable of suppression of variation and regulation of the threshold voltage has been proposed.
For example, Japanese Patent Laying-Open No. 2001-357680 discloses a scheme for preventing variation of the threshold voltages by repeating erase and write so as to gradually lower the threshold voltage. In this scheme, however, erase and write should be performed for each bit as well as a verify operation should be performed for each of these operations, which results in time-consuming data erase operation.
Meanwhile, Japanese Patent Laying-Open No. 06-028875 discloses a scheme for performing data write from an overerased state after all memory cells are set to the overerased state. Specifically, this publication proposes the scheme in which verify and write are performed while a non-selected word line is at a negative voltage during verify for cutting off-leakage of the memory cell in the overerased state. Namely, this publication discloses a scheme for regulating the threshold voltage such that the threshold voltage is within a certain range.
Japanese Patent Laying-Open No. 06-028875 discloses a scheme to regulate the threshold voltage of the selected memory cell by setting the non-selected word line to a negative voltage at the time of verify so as to suppress the off-leakage current. In general, however, in actual data read, the non-selected word line is set not to the negative voltage but to a ground voltage (0V). Therefore, even when the threshold voltage of the memory cell is regulated by sufficiently suppressing the off-leakage current at the time of verify, suppression of the off-leakage current is not sufficient under a condition of actual data read, that is, a condition in which the non-selected word line is set to 0V.